Notes for Everyone

Monday, 31 July 2017

CS6504 Nov Dec 2015 Important Questions

CS6504 Computer Graphics Regulation 2013 Guidance Materials

CS6504 CG Guidance Materials Regulation 2013

CS6504 Lecture Important Questions

CS6504 Part B Guidance Materials

CSE 5th Semester Anna University Important Questions

Regulation 2013 CS6504 CG expected Questions Part B Nov Dec 2015 Regulation 2013

Nov Dec 2015 Jan 2016 Important Questions Anna University

Nov Dec 2015 Jan 2016 CSE Important Questions Anna University

Nov Dec 2015 Jan 2016 IT Important Questions Anna University

Nov Dec 2015 Jan 2016 5th Semester Important Questions Anna University

Department of Computer Science and Engineering

Sub. Name: Computer Graphics                                                                   Sub.Code: CS6504

Max.Marks: 50                                                                                         Time: 90 min

Department: Computer Science and Engineering                             Sem/Year: V/III      Date:

Internal Assessment test II

PART – A

   Answer all the questions                                       5 x 2 =10

1.                                          What is uniform and differential scaling?(CO2)

2.               Define clipping .(CO2)

3.               What is shear? (CO2)

4.               What is called a convex hull?(CO3)

5.               Define viewing in 3D .(CO3)

             PART – B                                                       13 x 2 =26

6. Explain the window to viewport coordinate transformation. (CO2)13 (OR)

7. Explain Cohen-Sutherland Line clipping algorithm. (CO2) 13

8 With suitable examples, explain all 3D transformations (CO3)13 (OR)

9. Write notes on 3D viewing. (CO3) 13
                                                                    PART – C

10. (i) Clip the given line A(1,3) B(4,1) against a window P(2,2) Q(5,2) R(5,4) S(2,4) using Liang Barsky line clipping algorithm (CO2)

Department of Computer Science and Engineering

Sub. Name: Computer Graphics                                                                   Sub.Code: CS6504

Max.Marks: 50                                                                                         Time: 90 min

Department: Computer Science and Engineering                             Sem/Year: V/III      Date:

Internal Assessment test II

PART – A

   Answer all the questions                                       5 x 2 =10

1.            What is shear?(CO2)

2.            What is affine transformation?(CO2)

3.            What are the various polygon clipping algorithms?(CO2)

4.            Define quadric surfaces. (CO3)

5.            Define Octree.(CO3)

             PART – B                                                       13 x 2 =26

6. Discuss the various surface detection methods in detail.. (CO3)13 (OR)

7. Explain the various clipping operations (CO2) 13

1.   8 Explain the various polygon clipping algorithm. (CO2)13 (OR)

9. Differentiate parallel and perspective projections and derive their projection matrices (CO3) 13
                                                                    PART – C

10. (i) Clip the given line A(1,3) B(4,1) against a window P(2,2) Q(5,2) R(5,4) S(2,4) using Liang Barsky line clipping algorithm (CO2)

CS6303

CS6303 Nov Dec 2016 Important Questions

CS6303 Lecture Important Questions

CS6303 Part B Important Questions

Regulation 2013 CS6303 CA Important Questions Part B Nov Dec 2016

Regulation 2013 Nov Dec 2016 Important Questions Anna University

CS6303 Computer Architecture Important Questions Anna University

Nov Dec 2016 Important Questions Anna University

Department of Computer Science and Engineering

Sub. Name: Computer Architecture Sub.Code: CS6303

Max.Marks: 50 Time: 90 min

Department: Computer Science and Engineering Sem/Year: III/II Date:

Internal Assessment test III ( Unit IV and Unit V)

PART – A

Answer all the questions 5 x 2 =10

1. Define Spatial Locality(CO4)

2. What is Register Renaming? (CO4)

3. Write the formula to calculate the CPU time. (CO5)

4. What is temporal locality? (CO5)

5. Define Write Through. (CO5)

Part-B (40 marks)

6. Explain instruction level parallel processing. State the challenges of parallel processing.(CO4) (13)

Explain in details about the bus arbitration Techniques in DMA.(CO5) (13)

7. Explain the hardware multithreading.(CO4)13

Explain in detail about any two standard input and output interface required to connect the I/O device to the bus(CO5)13

Part C

8. Explain about the latest multicore processor with diagram.(CO4)

Department of Computer Science and Engineering

Sub. Name: Computer Architecture Sub.Code: CS6303

Max.Marks: 50 Time: 90 min

Department: Computer Science and Engineering Sem/Year: III/II Date:

Internal Assessment test III ( Unit IV and Unit V)

PART – A

Answer all the questions 5 x 2 =10

1. What is split transaction?(CO4)

2. Write the formula to average memory access time. (CO4)

3. List down the techniques used for reducing miss penalty (CO5)

4. What is page fault?(CO5)

5. Define cache. (CO5)

Part-B (40 marks)

4 Explain the SISD , MIMD, SIMD and SPMD systems.(CO4)13

What is virtual memory? Explain the steps involved in virtual memory address translation.(CO5)13

5 Elaborate on the various memory technologies and its relevance.(CO5)13

OR
Explain the hardware multithreading.(CO4)13

Part C

6. Explain about the latest multicore processor with diagram.(CO4)

CS6303 computer architecture

CS6303 Nov Dec 2016 Important Questions

CS6303 Lecture Important Questions

CS6303 Part B Important Questions

Regulation 2013 CS6303 CA Important Questions Part B Nov Dec 2016

Regulation 2013 Nov Dec 2016 Important Questions Anna University

CS6303 Computer Architecture Important Questions Anna University

Nov Dec 2016 Important Questions Anna University

Department of Computer Science and Engineering

Sub. Name: Computer Architecture Sub.Code: CS6303

Max.Marks: 50 Time: 90 min

Department: Computer Science and Engineering Sem/Year: III/II Date: 20.07.2017

Internal Assessment test I ( Unit I and II)

PART – A

Answer all the questions 5 x 2 =10

1. State the eight ideas of computer architecture .(CO1)

2. What is Pipeline?.(CO1)

3. Mention about auto decrement and Auto increment addressing mode? (CO1)

4. Define ALU.(CO2)

5. What is a CPU execution time for a Program?(CO2)

PART – B 13 x 2 =26

6. Explain the Components of computer system in detail. (CO1)13 (OR)

7. Explain briefly about the addressing mode (CO1) 13

8 Explain the algorithm for multiplication of two numbers with example. (CO1)13 (OR)

9. Explain the algorithm for floating point addition two numbers with example. (CO2) 13
PART – C

10. Why should we go from uniprocessor to multiprocessor. (CO1) 14 x 1 =14

CS6303 Computer Architecture

CS6303 Nov Dec 2016 Important Questions

CS6303 Lecture Important Questions

CS6303 Part B Important Questions

Regulation 2013 CS6303 CA Important Questions Part B Nov Dec 2016

Regulation 2013 Nov Dec 2016 Important Questions Anna University

CS6303 Computer Architecture Important Questions Anna University

Nov Dec 2016 Important Questions Anna University

Department of Computer Science and Engineering

Sub. Name: Computer Architecture Sub.Code: CS6303

Max.Marks: 50 Time: 90 min

Department: Computer Science and Engineering Sem/Year: III/II Date:

Unit II and III

Internal Assessment test II

PART – A

Answer all the questions 5 x 2 =10

1. What do mean by Subword Parallelism?(CO2)

2. How overflow occur in subtraction? (CO2)

3. Define processor cycle in pipelining. (CO3)

4. What is data path? (CO3)

5. Define structural hazards. (CO3)

Part-B (40 marks)

6. Explain different types of pipeline hazards with suitable example.(CO3) (13)

Explain in details how the exception are handled in MIPS architecture.(CO3) (13)

7. What are the major components required to execute MIPS instruction while building a datapath.(CO3)13

Discuss in detail about division algorithm in detail with diagram and examples. (Nov 2015)

Restoring Division Algorithm(CO2)13

Part C

8. Explain pipelined control of a latest system available in market with suitable block diagram.(CO3)

1. What is floating point numbers?(CO2)

2. Write the IEEE 754 floating point format. (CO2)

3. Define Pipeline speedup.(CO3)

4. What is a hazard? What are its types? (CO3)

5. Define structural hazards. (CO3)

Part-B (40 marks)

4 Explain the basic MIPS implementation with necessary multiplexers and control lines.(CO3)13

Describe the techniques for handling control hazards in pipelined datapath.(CO3)13

5 Describe subword parallelism in detail.(CO2)13

OR
What is data hazard? Explain the ways and means of handing it in pipelined datapath(CO3)13

Part C

6 Briefly Explain Carry Lookahead adder.(CO2)15

Saturday, 22 July 2017

R17 Anna University New Syllabus Regulation 2017-18 for affiliated Colleges

Anna University New Syllabus Regulation 2017-18 for affiliated Colleges Click Here

Anna University New Syllabus Regulation 2017-18 – Generating Employment Opportunities

Anna University is going to introduce a new syllabus Regulation which is applicable for the students who are going to join in the academic year 2017-18. Students who are pursuing degree now will follow the same Regulation which is currently held up. Main moto of this is to generate employment Opportunities for the Students.

Friday, 21 July 2017

EC6009 Advance Computer

EC6009 Advance Computer Architecture
Internal Assessment - I Key

PART – A

Answer all the questions 5 x 2 =10

1. State the formula for power dynamics .(CO1)

2. Define antidependence with example ?.(CO1)

3. How to measure the dependability? (CO1)

4. Define ALU.(CO2)

5. What is bandwidth and latency ?(CO2)

PART – B 16 x 2 =32

6. Give a brief explanation to avoid data dependence with dynamic scheduling. (CO2)16

7. Give a brief explanation of trends in Power , Energy and Cost. (CO1) 16

8 Give a brief explanation to avoid control dependence with hardware Speculation. (CO2)16

9. State and explain different generation of Computer (CO1) 16
PART – C

10. Give a brief explanation about different dependences in computer architecture. (CO2)8

Maximum:50Marks

Part-A (2*5=10Marks)

Define ALU

An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It represents the fundamental building block of the central processing unit (CPU) of a computer. Modern CPUs contain very powerful and complex ALUs.

DefineAnti Dependence with examples

A data dependency in computer science is a situation in which a program statement (instruction) refers to the data of a preceding statement. In compiler theory, the technique used to discover data dependencies among statements (or instructions) is called dependence analysis

Define measure of dependability

Dependability is a measure of a system's availability, reliability, and its maintainability, and maintenance support performance, and, in some cases, other characteristics such as durability, safety and security.

What is the formula for power dynamics

Power = Capacitive Load * Voltage ^ 2 * Frequency Switched.

What is bandwidth and latency

Latency (execution time): time to finish a fixed task • Throughput (bandwidth): number of tasks in fixed time • Different: exploit parallelism for throughput, not latency (e.g., bread) • Often contradictory (latency vs. throughput) • Will see many examples of this • Choose definition of performance that matches your goals • Scientific program: latency; web server: throughput?

Part-B (13*2=26 Marks)

a) Give a brief explanation to avoid data dependence with dynamic scheduling (16)
DIV.D F0,F2,F4
ADD.D F6,F0,F8
S.D F6,0(R1)
SUB.D F8,F10,F14
MULT.D F6,F10,F8

Give a brief explanation to avoid control dependence with hardware Speculation(16)

7. a)i)State and explain different generation of Computer (8)

S.N.	Generation & Description
1	First Generation The period of first generation: 1946-1959. Vacuum tube based.
2	Second Generation The period of second generation: 1959-1965. Transistor based.
3	Third Generation The period of third generation: 1965-1971. Integrated Circuit based.
4	Fourth Generation The period of fourth generation: 1971-1980. VLSI microprocessor based.
5	Fifth Generation The period of fifth generation: 1980-onwards. ULSI microprocessor based

Give a brief explanation of trends in Power , Energy and Cost(16)

Capacitance (C): To first order (i.e., the architect’s point of view rather than the more detailed view of a circuit designer), aggregate load capacitance largely depends on the wire lengths of on-chip structures. Supply voltage (V): For decades, supply voltage (V or Vdd) has dropped steadily with each technology generation Because of its direct quadratic influence on dynamic power, this has amazing leverage on power-aware design.

Activity factor (A): The activity factor is a fraction between 0 and 1 that refers to how often wires actually transition from 0 to 1 or 1 to 0. While the clock signal obviously switches at its full frequency, most other wires in the design have activity factors below 1. Strategies such as clock gating are used to save energy by reducing activity factors during a hardware unit’s idle periods

Clock frequency ( f ): The clock frequency has a fundamental and far-reaching impact on power dissipation. Not only does clock frequency directly influence power dissipation, but it also indirectly shapes power by its effect on supply voltage. Typically, maintaining higher clock frequencies may require (in part) maintaining a higher supply voltage

Dependencies between instructions

Q Instructions often depend on each other in such a way that a particular instruction cannot be executed until a preceding instruction or even two or three preceding instructions have been executed.

• 1 Data dependencies

• 2 Control dependencies

3 Resource dependencies

Data dependencies

i1: load r1, a

i2: load r2, b

i3: load r3, r1, r2

i4: mul r1, r2, r4;

i5: div r1, r2, r4

mul r1, r2, r3

Control dependencies

jz zproc

zproc: load r1, x

actual path of execution depends on the outcome of multiplication

impose dependencies on the logical subsequent instructions